Performance optimization of multiple memory architectures for DSP

Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of architecture are variable partitioning and scheduling. However there’s little research work that has been done on these problems. In this paper, we present a new graph model for tackling the variable partitioning problem, namely, Variable Independence Graph (VIG), which provides more precise information for variable partitioning compared to the previous graph models. We also present a scheduling algorithm, Rotation Scheduling with Variable Repartition (RSVR), that takes advantage of multiple memory modules. It’s a new scheduling technique based on retiming and software pipelining. It can re-partition the variables if necessary during the scheduling process. The experiment results show that the average improvement on schedule length by using the algorithm is 44.8%. Another major contribution of this paper is that we invented an algorithm for design space exploration on multiple memory architecture. Our approach produces more feasible solutions on a set of schedule length requirements, and less functional units in the solution for the same schedule length requirement, compared to the approach based on Interference Graph.